This application relies for priority upon Korean Patent Application No. 2001-24262, filed on May 4, 2001, the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention generally relates to the generation of internal command signals in a semiconductor memory device, and more specifically to the generation of internal command signals synchronized to an internal clock signal having a predetermined cycle time shorter than a cycle time of an external clock signal, such as from a test equipment.
2. General Background and Related Art
Many tests have been carried out on mass-produced synchronous dynamic random access memory (DRAM). When simultaneously testing many DRAM chips installed in a test equipment, an operation cycle time of a clock should be established that is much longer than a clock cycle of a normal operation in the synchronous DRAM in order to accomplish a regular transmission of signals between the test equipment and the DRAMs, because there is a large load capacitance at output terminals of the test equipment due to the testing of many DRAM chips.
A conventional internal command signal generating circuit in the semiconductor memory device is explained hereinafter.
FIG. 1 is a circuit diagram of a known arrangement for generating internal command signals in a semiconductor memory device. The conventional internal command signal generating circuit includes a buffer 10, a command signal decoder 20, an auto precharge unit 30, and a precharge unit 40. The buffer 10 generates internal control signals ICSb, IRASb, ICASb, and IWEb, internal address signal Ai[j], and buffered bank address signals B[0:3] in response to external clock signal CLK of the test equipment, external control signals /CS, /RAS, /CAS, and /WE, address signals A[0:n] of the DRAM, and bank address signals BA[0:1]. The command signal decoder 20 generates column active command signal COLACT, row active command signal ROWACT, and precharge command signal PRECHG in response to the internal control signals ICSb, IRASb, ICASb, and IWEb. The auto precharge unit 30 generates auto precharge signals APCGb[0:3] in response to the column active command signal COLACT, one of the internal address signals Ai[j], the buffered bank address signals B[0:3], and auto precharge control signal YBND_APCG for controlling an operation of the auto precharge, after a burst operation of read or write for one memory bank region is completed. The precharge unit 40 generates bank precharge signals PCGb[0:3] in response to the precharge command signal PRECHG, one of the internal address signals Ai[j], the buffered bank address signals B[0:3], and the auto precharge signals APCGb[0:3].
In the conventional internal command signal generator having the aforementioned structure, it is required that the cycle time of the external clock signal of the test equipment be much longer than the clock cycle time for normal operation of the synchronous DRAM, in case of simultaneously performing a test procedure for many chips of DRAMs installed in the test equipment. In this manner, the regular transmission with signals can be achieved. Briefly, because of setting the clock cycle time as described above, the testing time is consequently increased.
At least some of the inventions claimed herein provide circuits and methods for setting an internal clock signal to have a predetermined cycle time shorter than that of external clock signal of a test equipment, and generating internal command signals synchronized with the internal clock signal, thereby reduce a testing time that would otherwise be required.
According to an aspect of the present invention, there is provided an internal command signal generating circuit in a semiconductor memory device. The circuit includes a buffer for generating a plurality of internal control signals, a plurality of internal address signals, and a plurality of buffered bank address signals in response to external clock signal of a test equipment, a plurality of external control signals, a plurality of address signals, and a plurality of bank address signals. A command signal decoder composes the plurality of internal control signals and generates a test mode enable signal and a reversed test mode enable signal in response to a flag signal of the plurality of internal address signals for precharging all the bank, and composing the reversed test mode enable signal and the plurality of internal control signals and generating internal command signals of the semiconductor memory device. An auto precharge unit generates a plurality of auto precharge signals in response to the test mode enable signal, one of the plurality of internal address signals, the plurality of buffered bank address signals, auto precharge control signal, and one of the internal command signals of the semiconductor memory device. A precharge unit generates a plurality of bank precharge signals and bank precharge summation signal in response to the test mode enable signal, one of the plurality of internal address signals, the plurality of buffered bank address signals, the plurality of auto precharge signals, and one of the internal command signals of the semiconductor memory device. An internal clock generator generates first and second internal clocks when the test mode enable signal is enabled, and composes the test mode enable signal, the bank precharge summation signal, and one of the internal command signals of the semiconductor memory device and then generates a plurality of internal command control signals which synchronously respond to the first and second internal clock signals, wherein the command signal decoder composes the plurality of internal control signals and the reversed test mode enable signal and generates the internal command signals of the semiconductor memory device in response to the plurality of internal command control signals.
According to another aspect of this invention, there is provided a method for generating internal command signals in a semiconductor memory device, the method including: generating a plurality of internal control signals, a plurality of internal address signals, and a plurality of buffered bank address signals in response to external clock signal of a test equipment, a plurality of external control signals, a plurality of address signals, and a plurality of bank address signals; generating a test mode enable signal and a reversed test mode enable signal in response to a flag signal for precharging all the bank of the plurality of internal address signals; generating first and second internal clock signals when the test mode enable signal is enabled; composing the reversed test mode enable signal and the plurality of internal control signals and then generating internal command signals of the semiconductor memory device;
composing the test mode enable signal, one of the plurality of internal address signals, the plurality of buffered bank address signals, auto precharge control signal, and one of the internal command signals of the semiconductor memory device and then generating a plurality of auto precharge signals; composing the test mode enable signal, one of the plurality of internal address signals, the plurality of buffered bank address signals, the plurality of auto precharge signals, and one of the internal command signals of the semiconductor memory device, and then generating a plurality of bank precharge signals and bank precharge summation signal; and composing the test mode enable signal, the bank precharge summation signal, and one of the internal command signals of the semiconductor memory device and then generating a plurality of internal command control signals which synchronously respond to the first and second internal clock signals.
The foregoing features and advantages of the invention will be more fully explained, referring to the accompanying drawings.